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The Exascale: Why and How

Monday, January 10, 2011 - 9:30am - 10:30am
Keller 3-180
David Keyes (Columbia University)
Sustained floating-point computation rates on real applications, as
tracked by the ACM Gordon Bell Prize, increased by three orders of
magnitude from 1988 (1 Gigaflop/s) to 1998 (1 Teraflop/s), and by
another three orders of magnitude to 2008 (1 Petaflop/s). Computer
engineering provided only a couple of orders of magnitude of
improvement for individual cores over that period; the remaining
factor came from concurrency, which is approaching one million-fold.

Algorithmic improvements contributed meanwhile to making each flop
more valuable scientifically. As the semiconductor industry now slips
relative to its own roadmap for silicon-based logic and memory,
concurrency, especially on-chip many-core concurrency and GPGPU
SIMD-type concurrency, will play an increasing role in the next few
orders of magnitude, to arrive at the ambitious target of 1 Exaflop/s,
extrapolated for 2018. An important question is whether today's best
algorithms are efficiently hosted on such hardware and how much
co-design of algorithms and architecture will be required.

From the applications perspective, we illustrate eight reasons why
today's computational scientists have an insatiable appetite for such
performance: resolution, fidelity, dimension, artificial boundaries,
parameter inversion, optimal control, uncertainty quantification, and
the statistics of ensembles.

The paths to the exascale summit are debated, but all are narrow and
treacherous, constrained by fundamental laws of physics, cost, power
consumption, programmability, and reliability. Drawing on recent
reports, workshops, vendor projections, and experiences with
scientific codes on contemporary platforms, we propose roles for
today's researchers in one of the great global scientific quests of
the next decade.
MSC Code: 
82D37
Keywords: