Circuit Analysis Problems in High Frequency Digital Designs

Tuesday, November 25, 1997 - 2:00pm - 2:30pm
Keller 3-180
Tuyen Nguyen (IBM)
In this talk, we will discuss some problems of circuit analysis in the context of high frequency digital designs, especially microprocessor design. In particular, we will discuss the following algorithmic problems: linear model reduction for timing and noise analyis, model reduction for distributed circuits, simulation of nonlinear circuits with regular structures like memory or array circuits, computing bounds on the responses of general linear systems for noise avoidance.

This is joint work with Eli Chiprout and Anirudh Devgan.