On the Stability of Partial Element Equivalent Circuits for the Electromagnetic Modeling of VLSI Interconnects

Tuesday, November 25, 1997 - 9:30am - 10:00am
Keller 3-180
Albert Ruehli (IBM)
The Partial Element Equivalent Circuit (PEEC) model technique is an approach for the modeling of tree dimensional geometries. One of the applications is the modeling of VLSI interconnects on chips and packages. For these problems time-domain solutions are of interest. We will give examples of time-domain PEEC models. However, the stability of these models is not guaranteed since so called late-time instabilities may occur. We will give some insight into the problem at hand and we will outline a pseudospectral technique for observing the roots which are responsible for the instabilities.

This is joint work with Jane Cullum.