I will describe and discuss our modelling and simulation efforts for thin film deposition in the metallization stages for fabrication of integrated circuits. Our main work has been to use a continuum model for feature-scale deposition using level set methods for the topography evolution. Validation with both experiment and Monte Carlo simulations has proved extremely fruitful in how we improve the continuum model and enhance its predictive capability.
Using 3D simulations we are now able to study across-wafer variations in step coverage of barrier and seed layers. To obtain the correct angular distribution of arriving flux required the additional development of a reactor-scale model to account for scattering in the gas phase. Together, these two simulation tools enable us now to optimize physical vapor deposition processes for given macroscopic controls (target erosion for magnetron sputtering, target-substrate distance, gas pressure and temperature, substrate bias etc.).
This is joint work with Frieder Baumann, George Gilmer and Jacques Dalla Torre of Bell Labs as well as Chan-Soo Shin, Ivan Petrov and Tae-Yoon Lee of the University of Illinois, Urbana-Champaign.
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