Inclusion of parasitic effects due to interconnects becomes essential when simulating modern high-speed high-density circuits at the chip or board level. Usually, the accurate extraction of interconnects out of the layout yields linear time-invariant subnets consisting of resistors, capacitors, and inductors. Unfortunately, these nets may become so large that their inclusion into standard circuit simulation tasks is inefficient or even prohibitive.

By the determination of a few leading eigenvalues of the matrices describing linear subnets it is possible to reduce the simulation costs. We modified the so called Jakobi Davidson algorithm for generalized eigenproblems in order to achieve a better efficiency for the symmetric positive definite problems arising in this framework. The presentation describes this algorithm together with the reduction ansatz.

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